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CAT64LC40 4 kb SPI Serial EEPROM
Description
The CAT64LC40 is a 4 kb Serial EEPROM which is configured as 256 registers by 16 bits. Each register can be written (or read) serially by using the DI (or DO) pin. The CAT64LC40 is manufactured using ON Semiconductor's advanced CMOS EEPROM floating gate technology. It is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin DIP, SOIC and TSSOP packages.
Features
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* * * * * * * * * * * *
SPI Bus Compatible Low Power CMOS Technology 2.5 V to 6.0 V Operation Self-Timed Write Cycle with Auto-Clear Hardware Reset Pin Hardware and Software Write Protection Commercial, Industrial and Automotive Temperature Ranges Power-up Inadvertent Write Protection RDY/BSY Pin for End-of-Write Indication 1,000,000 Program/Erase Cycles 100 Year Data Retention This Device is Pb-Free, Halogen Free/BFR Free and RoHS Compliant*
VCC GND Pin Name MEMORY ARRAY 256 x 16 ADDRESS DECODER CS SK DI DO DATA REGISTER DI OUTPUT BUFFER MODE DECODE LOGIC VCC GND RESET RDY/BUSY
PDIP-8 P, L SUFFIX CASE 646AA
SOIC-8 J, W, S, V SUFFIX CASE 751BD
TSSOP-8 U, Y SUFFIX CASE 948AL
PIN FUNCTION
Function Chip Select Clock Input Serial Data Input Serial Data Output +2.5 V to +6.0 V Power Supply Ground Reset Ready/BUSY Status
RESET CS
SK
CLOCK GENERATOR
DO
RDY/BUSY
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet.
Figure 1. Block Diagram
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2009
September, 2009 - Rev. 4
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Publication Order Number: CAT64LC40/D
CAT64LC40
PIN CONNECTIONS
CS SK DI DO 1 2 3 4 8 7 6 5 VCC RDY/BUSY RESET GND RDY/BUSY VCC CS SK 1 2 3 4 8 7 6 5 RESET GND DO DI CS SK DI DO 1 2 3 4 8 7 6 5 VCC RDY/BUSY RESET GND
PDIP-8 (P, L) CS SK DI DO
SOIC-8 (J, W) 1 2 3 4 8 7 6 5 VCC RDY/BUSY RESET GND
TSSOP-8 (U, Y)
SOIC-8 (S, V)
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to Ground (Note 1) VCC with Respect to Ground Package Power Dissipation Capability (TA = 25C) Lead Soldering Temperature (10 secs) Output Short Circuit Current (Note 2) Ratings -55 to +125 -65 to +150 -2.0 to +VCC +2.0 -2.0 to +7.0 1.0 300 100 Unit C C V V W C mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The minimum DC input voltage is -0.5 V. During transitions, inputs may undershoot to -2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns. 2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS
Symbol NEND (Note 3) TDR (Note 3) VZAP (Note 3) ILTH (Notes 3 and 4) Endurance Data Retention ESD Susceptibility Latch-Up Parameter Min 1,000,000 100 2000 100 Max Units Cycles/Byte Years V mA
3. This parameter is tested initially and after a design or process change that affects the parameter. 4. Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1 V to VCC +1 V.
Table 3. CAPACITANCE (TA = 25C, f = 1.0 MHz, VCC = 6.0 V)
Symbol CI/O (Note 5) CIN (Note 5) Test Input/Output Capacitance (DO, RDY/BSY) Input Capacitance (CS, SK, DI, RESET) Conditions VI/O = 0 V VIN = 0 V Max 8 6 Units pF pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
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CAT64LC40
Table 4. D.C. OPERATING CHARACTERISTICS (VCC = +2.5 V to +6.0 V, unless otherwise specified.)
Limits Symbol ICC ICCP ISB (Note 6) ILI ILO VIL VIH VIL VIH VOH (Note 6) Parameter Operating Current EWEN, EWDS, READ Program Current 2.5 V 6.0 V 2.5 V 6.0 V Standby Current Input Leakage Current Output Leakage Current Low Level Input Voltage, DI High Level Input Voltage, DI Low Level Input Voltage, CS, SK, RESET High Level Input Voltage, CS, SK, RESET High Level Output Voltage 2.5 V 6.0 V IOH = -10 mA IOH = -10 mA IOH = -400 mA VOL (Note 6) Low Level Output Voltage 2.5 V 6.0 V 6. VOH and VOL spec applies to READY/BUSY pin also. IOL = 10 mA IOL = 2.1 mA VIN = GND or VCC CS = VCC VIN = GND to VCC VOUT = GND to VCC -0.1 VCC x 0.7 -0.1 VCC x 0.8 VCC - 0.3 VCC - 0.3 2.4 0.4 0.4 Test Conditions fSK = 250 kHz fSK = 1 MHz Min Typ Max 0.4 1 2 3 3 2 10 VCC x 0.3 VCC + 0.5 VCC x 0.2 VCC + 0.5 Units mA mA mA mA mA mA mA V V V V V V V V V
Table 5. A.C. OPERATING CHARACTERISTICS (VCC = +2.5 V to +6.0 V, unless otherwise specified.)
Limits Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ (Note 7) tCSMIN tSKHI tSKLOW tSV fSK tRESS tRESMIN tRESH tRC CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High Impedance Minimum CS High Time Minimum SK High Time 2.5 V 4.5 V - 6.0 V Minimum SK Low Time 2.5 V 4.5 V - 6.0 V Output Delay to Status Valid Maximum Clock Frequency 2.5 V 4.5 V - 6.0 V Reset to CS Setup Time Minimum RESET High Time RESET to READY Hold Time Write Recovery 250 1000 0 250 0 100 ns ns ns ns 250 1000 400 1000 400 500 ns kHz ns Parameter Min 100 100 200 200 300 300 500 Typ Max Units ns ns ns ns ns ns ns ns ns
7. This parameter is sampled but not 100% tested.
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CAT64LC40
Table 6. POWER-UP TIMING (Notes 8 and 9)
Symbol tPUR tPUW Power-Up to Read Operation Power-Up to Program Operation Parameter Min Max 10 1 Units ms ms
8. This parameter is tested initially and after a design or process change that affects the parameter. 9. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Table 7. WRITE CYCLE LIMITS
Symbol tWR Program Cycle Time Parameter 2.5 V 4.5 V - 6.0 V Min Max 10 5 Units ms
Table 8. INSTRUCTION SET
Instruction Read Write Write Enable Write Disable [Write All Locations] (Note 10) Opcode 10101000 10100100 10100011 10100000 10100001 Address A7 A6 A5 A4 A3 A2 A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 XXXXXXXX XXXXXXXX XXXXXXXX D15 - D0 Data D15 - D0 D15 - D0
10. (Write All Locations) is a test mode operation and is therefore not included in the AC/DC Operations specifications.
VCC x 0.8 INPUT PULSE LEVELS VCC x 0.2
VCC x 0.7 VCC x 0.3
REFERENCE POINTS
Figure 2. AC Testing Input/Output Waveform (Notes 11, 12 and 13) (CL = 100 pF)
11. Input Rise and Fall Times (10% to 90%) < 10 ns. 12. Input Pulse Levels = VCC x 0.2 and VCC x 0.8. 13. Input and Output Timing Reference = VCC x 0.3 and VCC x 0.7.
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CAT64LC40
Device Operation The CAT64LC40 is a 4 kb nonvolatile memory intended for use with all standard controllers. The CAT64LC40 is organized in a 256 x 16 format. All instructions are based on an 8-bit format. There are four 16-bit instructions: READ, WRITE, EWEN, and EWDS. The CAT64LC40 operates on a single power supply ranging from 2.5 V to 6.0 V and it has an on-chip voltage generator to provide the high voltage needed during a programming operation. Instructions, addresses and data to be written are clocked into the DI pin
RESET tRESS SK tDIS DI tCSS CS tPD0, tPD1 DO tRC RDY/BUSY tRESH tSV tHZ tSV tCSH tCSMIN tDIH tSKLOW tSKHI
on the rising edge of the SK clock. The DO pin is normally in a high impedance state except when outputting data in a READ operation or outputting RDY/BSY status when polled during a WRITE operation. The format for all instructions sent to this device includes a 4-bit start sequence, 1010, a 4-bit op code and an 8-bit address field or dummy bits. For a WRITE operation, a 16-bit data field is also required following the 8-bit address field.
Figure 3. Synchronous Data Timing
RESET
SK
CS
DI
1
0
1
0
1
0
0
0
ADDRESS*
DO HIGH
D15 D14
D1 D0
RDY/BUSY
Figure 4. Read Instruction Timing
*Please check the instruction set table for address
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CAT64LC40
The CAT64LC40 requires an active LOW CS in order to be selected. Each instruction must be preceded by a HIGH-to-LOW transition of CS before the input of the 4-bit start sequence. Prior to the 4-bit start sequence (1010), the device will ignore inputs of all other logical sequence.
Read Write
Upon receiving a READ command and address (clocked into the DI pin), the DO pin will output data one tPD after the falling edge of the 16th clock (the last bit of the address field). The READ operation is not affected by the RESET input.
RESET
After receiving a WRITE op code, address and data, the device goes into the AUTO-Clear cycle and then the WRITE cycle. The RDY/BSY pin will output the BUSY status (LOW) one tSV after the rising edge of the 32nd clock (the last data bit) and will stay LOW until the write cycle is complete. Then it will output a logical "1" until the next WRITE cycle. The RDY/BSY output is not affected by the input of CS.
SK
CS
DI
1
0
1
0
0
1
0
0
ADDRESS*
D15
D0
DO
RDY/BUSY
Figure 5. Write Instruction Timing
*Please check instruction set table for address.
RESET
LOW
SK
CS WRITE INSTRUCTION DI NEXT INSTRUCTION
DO HIGH
RDY/BUSY
Figure 6. Ready/BUSY Status Instruction Timing
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CAT64LC40
An alternative to get RDY/BSY status is from the DO pin. During a write cycle, asserting a LOW input to the CS pin will cause the DO pin to output the RDY/BSY status. Bringing CS HIGH will bring the DO pin back to a high impedance state again. After the device has completed a WRITE cycle, the DO pin will output a logical "1" when the device is deselected. The rising edge of the first "1" input on the DI pin will reset DO back to the high impedance state again. The WRITE operation can be halted anywhere in the operation by the RESET input. If a RESET pulse occurs during a WRITE operation, the device will abort the operation and output a READY status. NOTE: Data may be corrupted if a RESET occurs while the device is BUSY. If the reset occurs before the BUSY period, no writing will be initiated. However, if RESET occurs after the BUSY period, new data will have been written over the old data.
RESET
SK
CS
DI
1
0
1
0
0
1
0
0
ADDRESS*
D15
D0
DO tWR RDY/BUSY *Please check instruction set table for address.
Figure 7. RESET During BUSY Instruction Timing
RESET
SK
CS
DI
1
0
1
0
0
0
1
1
DO
HIGH-Z
RDY/BUSY
HIGH
Figure 8. EWEN Instruction Timing
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CAT64LC40
Reset Erase/Write Enable and Disable
The RESET pin, when set to HIGH, will reset or abort a WRITE operation. When RESET is set to HIGH while the WRITE instruction is being entered, the device will not execute the WRITE instruction and will keep DO in High-Z condition. When RESET is set to HIGH, while the device is in a clear/write cycle, the device will abort the operation and will display READY status on the RDY/BSY pin and on the DO pin if CS is low. The RESET input affects only the WRITE and WRITEALL operations. It does not reset any other operations such as READ, EWEN and EWDS.
The CAT64LC40 powers up in the erase/write disabled state. After power-up or while the device is in an erase/write disabled state, any write operation must be preceded by an execution of the EWEN instruction. Once enabled, the device will stay enabled until an EWDS has been executed or a power-down has occurred. The EWDS is used to prevent any inadvertent over-writing of the data. The EWEN and EWDS instructions have no affect on the READ operation and are not affected by the RESET input.
RESET
SK
CS
DI
1
0
1
0
0
0
0
0
DO
HIGH-Z
RDY/BUSY
HIGH
Figure 9. EWDS Instruction Timing
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CAT64LC40
PACKAGE DIMENSIONS
PDIP-8, 300 mils CASE 646AA-01 ISSUE A
SYMBOL A A1 A2 b E1 b2 c D E E1 e eB PIN # 1 IDENTIFICATION D L 7.87 2.92 3.30 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 BSC 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25 7.11 MIN NOM MAX 5.33
TOP VIEW E
A
A2
A1 b2 L c
e SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001.
b
eB
END VIEW
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CAT64LC40
PACKAGE DIMENSIONS
SOIC 8, 150 mils CASE 751BD-01 ISSUE O
SYMBOL A A1 b c E1 E D E E1 e h L PIN # 1 IDENTIFICATION TOP VIEW 0.25 0.40 MIN 1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.50 1.27 NOM MAX 1.75 0.25 0.51 0.25 5.00 6.20 4.00
0
8
D
h
A1
A
c e SIDE VIEW b L END VIEW
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012.
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CAT64LC40
PACKAGE DIMENSIONS
TSSOP8, 4.4x3 CASE 948AL-01 ISSUE O
b
SYMBOL
A A1 A2 b E1 E c D E E1 e L L1
MIN
0.05 0.80 0.19 0.09 2.90 6.30 4.30
NOM
MAX
1.20 0.15
0.90
1.05 0.30 0.20
3.00 6.40 4.40 0.65 BSC 1.00 REF
3.10 6.50 4.50
0.50
0.60
0.75
e
0
8
TOP VIEW D
A2
A
q1
c
A1 SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153.
L1 END VIEW
L
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CAT64LC40
Example of Ordering Information
Prefix CAT Device # 64LC40 Suffix V I -G T3
Company ID Product Number 64LC40
Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) A = Automotive (-40C to +105C)* Lead Finish G: NiPdAu Blank: Matte-Tin
Tape & Reel (Note 18) T3: 3,000 / Tape & Reel
Package P: PDIP S: SOIC (JEDEC) J: SOIC (JEDEC) U: TSSOP L: PDIP (Lead free, Halogen free) V: SOIC (JEDEC) (Lead free, Halogen free) W: SOIC (JEDEC) (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free)
*-40C to +125C is available upon request.
ORDERING INFORMATION
Orderable Part Number (for Pb-Free Devices) CAT64LC40LI-GT3 CAT64LC40VI-GT3 CAT64LC40WI-GT3 CAT64LC40YI-GT3 14. All packages are RoHS-compliant (Lead-free, Halogen-free). 15. The standard lead finish is NiPdAu. 16. The device used in the above example is a 64LC40VI-GT3 (SOIC, Industrial Temperature, Tape & Reel). 17. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 18. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CAT64LC40/D

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